Virtual memory translator for real-time operating systems
US7558940B2 · kind B2 · utility
2Cited by
5References
6Claims
0Family size
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Key dates
| Filing date | Feb 23, 2007 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Aug 17, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-tiered lookup table is used to progressively map a virtual address to a specific control word that facilitates resolution of the virtual address for a translation lookaside buffer (TLB) miss. In one embodiment, the control word has a compressed and efficiently encoded image of the TLB hardware register data. The control word is accessed with or without a level of indirection in various embodiments. In some embodiments, the control word provides all information needed to decode the majority of memory blocks, or points to a third level for special blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.