Automatic detection of micro-tile enabled memory
US7558941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | May 1, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0813
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a write cache line with a unique bit pattern is written into memory in a memory channel at a starting address. An attempt is made to enable micro-tile memory accesses into each memory integrated circuit on memory modules in the memory channel. A read cache line is read from memory in the memory channel at the starting address. The bit patterns of the read cache line and the write cache line are compared. If in the comparison it is determined that the bit pattern of the read cache line differs from the write cache line, then micro-tile memory access is enabled into each memory integrated circuit on memory modules in the memory channel. If in the comparison it is determined that the bit pattern of the read cache line is the same as the bit pattern of the write cache line, then micro-tile memory access is not supported and cannot be enabled in each memory integrated circuit on memory modules in the memory channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.