Patent · US Active

Charge modulation network for multiple power domains for silicon-on-insulator technology

US7560778B2 · kind B2 · utility

2Cited by
13References
15Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 12, 2006
Grant dateJul 14, 2009
Priority date
Expiry dateJan 19, 2027

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D89/601

Abstract

An SOI integrated circuit includes ESD protection on an SOI chip. A first power domain and a second power domain are provided in the SOI chip. In one embodiment, a charge modulation network in the SOI chip between the first power domain and the second power domain mitigates accumulation of electrical charge in an electrically isolated region of the SOI chip. In another embodiment, an ESD protection device in the SOI chip electrically connects the first power domain and the second power domain via a low metal layer to provide a discharge path for accumulated charge.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.