High-speed CML circuit design
US7560957B2 · kind B2 · utility
35Cited by
17References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2006 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Jul 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01707
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.