Multi-loop data weighted averaging in a delta-sigma DAC
US7561088B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 2008 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Apr 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses enable generating an analog representation of an M-bit digital input. A DAC system receives the M-bit data word and generates a control signal to control the output elements of a DAC to output an analog representation of the input data word. The DAC includes two data weighted averaging (DWA) loops, each one having 2M bits to control corresponding groups of 2M output elements. The control signal includes a number of bits equal to the number of output elements, with a number of one bits equal to the number of output elements to activate to represent the input data word. Half of the number of ones are triggered by one of the DWA loops, and the other half are triggered by the other DWA loop. One of the loops may include a constant offset in addition to the variable number of ones that represents the input data word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.