Apparatus and method for adjusting a pixel clock frequency based on a phase locked loop
US7561205B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 28, 2005 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Jan 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for adjusting a pixel clock frequency based on a phase locked loop (PLL) includes: a pixel clock generator (11) for generating an actual pixel clock having an actual frequency; a division frequency counter (12) for dividing the actual pixel clock into several pixel clocks having different frequency ranges by means of multiplying the actual frequency of the actual pixel clock by a multiplier; a reference frequency counter (13) for dividing the actual pixel clock by means of lowering the actual frequency of the actual pixel clock, and generating a reference frequency; a reactive frequency counter (14) for dividing the actual pixel clock by means of heightening the actual frequency of the actual pixel clock, and generating a reactive frequency; a PLL circuit (16) for integrating the reference frequency and the reactive frequency to generate a required pixel clock having a required frequency. A related method is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.