Protection circuit in semiconductor circuit device comprising a plurality of chips
US7561390B2 · kind B2 · utility
5Cited by
8References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 8, 2005 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Dec 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip package according to an embodiment of the invention comprises a first chip and a second chip. A first ground line formed in the first chip and the second ground line formed in the second chip are connected via ESD protection circuits. One of the protection circuits is formed in the first chip and the other is formed in the second chip, allowing effective ESD discharge according to CDM model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.