Verification apparatus, verification method, and program
US7561999B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2004 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Feb 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A verification apparatus that efficiently performs hardware verification and software verification in the development of a system LSI with great accuracy. At the hardware verification, an equivalence verification section compares the result of the simulation of an HDL model by a logic simulator and an expected value generated from an expected value calculation model and verifies whether there is equivalence between them. At the software verification, the expected value calculation model is used via an interface section and a firmware is verified by a software debugger. The expected value calculation model is used as an expected value generation model at hardware verification time and is used as a C model of hardware at software verification time. By using the expected value calculation model both for the hardware verification and for the software verification in this way, verification can efficiently be performed with great accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.