DRAM controller for graphics processing operable to enable/disable burst transfer
US7562184B2 · kind B2 · utility
225Cited by
9References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Nov 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1042
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.