Design verification for a switching network logic using formal techniques
US7562322B2 · kind B2 · utility
3Cited by
7References
17Claims
0Family size
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Key dates
| Filing date | Apr 16, 2007 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Aug 22, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the design may be generated and model checking applied to the abstraction. Results obtained using these techniques may be extended by performance analysis and/or verification of sequential operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.