Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit
US7563687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2005 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Apr 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (21); Deposit of a first insulator layer (31) on the first metallic layer (21); Deposit of a second metallic layer (41) on the first insulator layer (31); Formation of an upper electrode (4) in the second layer metallic (41); Deposit of a second insulator layer (13) covering the upper electrode (4); Etching of the second insulator layer to form a spacer (14) on this first insulator layer surrounding the upper electrode (4); then Formation of a lower electrode (2) and a dielectric (3) by removal of parts from the first metallic layer and insulator not covered by the upper electrode (4) or the spacer (14); and Formation of an interconnection line (5). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.