Semiconductor device
US7564093B2 · kind B2 · utility
7Cited by
2References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2006 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Jun 22, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
Abstract
A semiconductor device comprises static random access memory (SRAM) cells formed in a semiconductor substrate, first deep trenches isolating each boundary of an n-well and a p-well of the SRAM cells, second deep trenches isolating the SRAM cells into each unit bit cell, and at least one or more contacts taking substance voltage potentials in regions isolated by the first and second deep trenches. Then, the device becomes possible to improve a soft error resistance without increasing the device in size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.