Fully testable surface mount die package configured for two-sided cooling
US7564128B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 2007 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Nov 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power semiconductor die is sandwiched between upper and lower heat conducting laminate structures to form a surface mount component that is configured for double-sided cooling. The upper heat conducting laminate structure electrically couples top-side die terminal(s) to conductors formed on the inboard face of the lower heat conducting laminate structure, and all of the die terminals are electrically coupled to conductors formed on the outboard face of the lower heat conducting laminate structure. The die package can be placed in a test fixture for full power testing, and when installed in an electronic assembly including a circuit board and upper and lower heatsinks, the die is thermally coupled to the upper heatsink through the upper heat conducting laminate structure, and to the lower heatsink through the circuit board and the lower heat conducting laminate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.