Peak hold circuit, motor drive control circuit having the peak hold circuit and motor apparatus having the motor drive control circuit
US7564207B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 2005 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Jun 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02P6/15
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A peak hold circuit is provided that operates stably even if a peak voltage to be held of a motor-drive-current detection voltage is minute. The peak hold circuit includes: a level shift circuit shifting the motor-drive-current detection voltage by a given voltage; a differential amplifier circuit receiving an output voltage of the level shift circuit and a voltage at an output terminal to amplify and output a difference between the voltages; an output transistor receiving at its base an output voltage of the differential amplifier circuit and outputting from its emitter charging current; a capacitor charged with the charging current to hold the voltage at the output terminal; a bias element generating a voltage substantially equal to the given voltage of the level shift circuit; and a resistance element provided between the bias element and the output terminal for controlling discharging current of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.