Flash memory device and writing method thereof
US7564712B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2007 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Aug 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device includes a memory cell array including a plurality of memory cells. A data writing buffer temporarily stores data to be written into the memory cells. A control circuit controls a write operation of the memory cells. A decoder decodes write address of the memory cell in response to the control circuit and regulating a constant current to flow through a selected bit line with reference to a result of the decoding. The decoder decodes an address and controls a current in units of a memory cell during a normal writing mode and decodes an address and controls a current in units of a memory block during a test writing mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.