Process and electronic decoding circuit for a diphase asynchronous frame whose length is not known in advance, corresponding application, computer programme and storage means
US7564936B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Nov 19, 2004 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Jun 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M5/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoding process, by an electronic circuit of a diphase asynchronous frame carried by an encoded data signal and comprising L information bits followed by at least one stop bit. The process comprises a step for automatically detecting the length L in information bits of the frame so as to decode the entire frame, the length L of the frame being variable from one frame to another and such that Lmin≦L≦Lmax=(Lmin+k), where k is a predetermined whole number greater than or equal to one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.