Apparatus and method for increasing readout speed of a solid state imager
US7565033B2 · kind B2 · utility
19Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2002 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Aug 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An imaging system features high speed digitization of pixel signals by utilizing top and bottom digitization circuits which pipeline sample-and-hold operations with analog-to-digital conversion. In operation, while one digitization circuit is performing a sample-and-hold operation, the other digitization circuit is performing analog-to-digital conversion. The speed of the imaging system may be further increased by pipelining and interleaving operations within the top and bottom digitization circuits by using additional sets of sample-and-hold circuits and analog-to-digital converters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.