Clock noise canceling circuit
US7565121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2006 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Feb 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/00307
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a clock noise canceling circuit, a coupler extracts a signal from a clock signal. A filter selects a harmonic component of a preset frequency in the extraction signal from the coupler. A phase shifter phase inverts the harmonic component of the preset frequency from the filter. An AGC amplifier amplifies the phase-inverted harmonic component from the phase shifter. Also, a combiner combines the amplified component from the phase shifter with the clock signal to eliminate the harmonic component of the preset frequency from the clock signal. A power detector detects a power level of the harmonic component of the preset frequency in an output signal of the combiner. Additionally, a controller controls gain of the automatic gain control amplifier based on the power level of the harmonic component detected by the power detector, thereby canceling noises.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.