Patent · US Active

Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devices

US7565390B1 · kind B1 · utility

2Cited by

3References

26Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Tat Mun Lui · Petaling Jaya, MY
Bee Yee Ng · Bandar Jengka, MY
Jun Tan · Kepong, MY
Boon Jin Ang · Butterworth, MY

Key dates

Filing date	Mar 23, 2005
Grant date	Jul 21, 2009
Priority date	—
Expiry date	Jan 12, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F7/4991
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

In circuitry such as a programmable logic device (“PLD”), each of several multiplier blocks includes partial products generation circuitry and partial products addition circuitry. Two such multiplier blocks can be used together to provide multiply-accumulate (“MAC”) capability. The partial products addition circuitry in one of the paired blocks is used to add each successive product produced by the other paired block to a previous accumulation of products in the first-mentioned paired block. Provisions are also made for accumulating any overflow from operation of the partial products addition circuitry in the first-mentioned paired block.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.