Layered crossbar for interconnection of multiple processors and shared memories
US7565475B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2006 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Aug 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17375
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods are disclosed for processing memory transaction requests and memory transaction results between multiple processors and multiple shared memories, where the communications path between the multiple processors and shared memories is provided by a multi-stage crossbar network comprising a plurality of serially interconnected crossbar switches, wherein each of the crossbar switches independently assigns local memory transaction identifiers to each memory transaction request that it processes and uses the local memory transaction identifiers to match each received memory transaction result with its corresponding previously processed memory transaction request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.