Fast parity scan of memory arrays
US7565597B1 · kind B1 · utility
6Cited by
2References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2005 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Jul 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel method for scanning bit parity in a memory array, and a circuit for implementing it, are disclosed. In a memory array that has one or more rows of memory cells, the method for checking data parity includes storing a plurality of data bits in the memory cells, scanning a row of memory cells independently of a memory read operation to ascertain the stored data bits; and determining parity for the row of memory cells by the results of the scanning. The method is accomplished by means of a dedicated parity scanning circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.