Patent · US Active

Massively parallel boolean satisfiability implication circuit

US7565634B1 · kind B1 · utility

6Cited by
3References
10Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 20, 2005
Grant dateJul 21, 2009
Priority date—
Expiry dateOct 22, 2026

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG05B2219/23279
  • WIPO fieldControl
  • WIPO sectorInstruments

Abstract

The application concerns prototyped custom Programmable Logic Devices (Pills) for Boolean satisfiability (SAT) problems. This approach is based on the use of clause evaluation circuits (CECs), which indicate whether or not a single variable of the clause is asserted by the clause, and variable evaluation circuits (VECs), which identify the asserted variable of a clause having exactly one variable asserted by the clause. Scaling is provided by the use of partial CEC and VEC circuits.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.