Multi-channel, multi-service debug on a pipelined CPU architecture
US7565644B2 · kind B2 · utility
5Cited by
20References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 11, 2005 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Nov 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for debugging an executing service on a pipelined CPU architecture are described. In one embodiment, a breakpoint within an executing service is set and a minimum state of the executing service is saved. In addition, a program counter of the executing service is altered. The program counter is restored and the state of the executing service is restored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.