Devices with adjustable dual-polarity trigger- and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated circuits

US7566914B2 · kind B2 · utility

Assignees

• Intersil Americas LLC · US
• University of Central Florida · US

Inventors

• Javier Alejandro Salcedo · North Billerica, US
• Juin J. Liou · Oviedo, US
• Joseph C. Bernier · Peoria, US
• Donald K. Whitney · Melbourne, US

Key dates

• Filing date: Nov 30, 2005
• Grant date: Jul 28, 2009
• Expiry date: Jul 28, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D8/80

Abstract

Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2 standard for ESD immunity. ESD protection performance is demonstr…