Guard ring extension to prevent reliability failures
US7566915B2 · kind B2 · utility
13Cited by
0References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2006 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Jul 20, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/07
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.