On-chip circuit pad structure
US7566952B2 · kind B2 · utility
4Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2005 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Jul 28, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Shielded circuit pad is provided where the parasitic capacitance is tuned out by the inclusion of a shunt transmission line stub which reduces the substrate induced loss in millimeter-wave applications. The circuit pad is located on the substrate, with a shield located beneath the circuit pad, and the shunt transmission line stub attached to the circuit pad. Accordingly, controlled impedance is obtained for millimeter-wave applications. The spacing between the circuit pad and the shield may then be minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.