Tri-stated driver for bandwidth-limited load
US7567094B2 · kind B2 · utility
3Cited by
15References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 25, 2007 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | May 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS driver circuit is configured to provide a tri-state condition after a predetermined number of like-valued data bits have been transmitted, reducing the presence of intersymbol interference (ISI) along a transmission channel. In situations where the transmission channel is bandwidth-limited, the use of the tri-stating technique allows for the complete transition to the supply rails during the given bit period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.