Symmetrical differential amplifier
US7567124B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2007 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Sep 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45674
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential amplifier has improved power efficiency, reduced offset penalty and a symmetrical output differential signal. Such a differential amplifier may include: (a) a bias circuit that has a first input device and a second input device; (b) a first load device and a second load device, each biased by a bias voltage from the bias circuit; and (c) a third input device and a fourth input device that are connected in series with the first load device and the second load device, respectively. In that differential amplifier, the differential input signal is applied across the first and second input devices, as well as across the third and the fourth input devices. The first, second, third and fourth input devices are sized such that a total current in the first and second input devices bears a predetermined ratio to a total current in the third and fourth input devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.