Multilayer chip capacitor
US7567425B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2008 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Dec 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G4/38
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units; and first to fourth outer electrodes, wherein the first capacitor unit includes at least one pair of first and second inner electrodes, the second capacitor unit includes at least one pair of third and fourth inner electrodes, an alternate laminated portion is formed in one area within the capacitor body, the alternate laminated portion having the first to fourth inner electrodes sequentially laminated therein, and a capacitance adjusting portion is formed in another area within the capacitor body, the capacitance adjusting portion having at least one of the one pair of first and second inner electrodes and the one pair of third and fourth inner electrodes laminated repeatedly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.