Semiconductor memory device and testing method thereof
US7567476B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2006 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Oct 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes mini arrays and a serial-parallel conversion circuit. The serial-parallel conversion circuit simultaneously writes two continuous data into mutually different mini arrays out of plural data that are continuously input synchronously with an internal clock, and continuously outputs two data simultaneously read from different mini arrays, synchronously with the internal clock. In testing the semiconductor memory device according to the present invention, one data is written during a period when an external clock having a cycle of an integer times cycle of the internal clock is fixed to a high level or a low level. With this arrangement, continuous data can be assigned to mutually different mini arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.