Method and system for realizing a logic model design
US7567892B2 · kind B2 · utility
2Cited by
7References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Jun 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques directed to realizing and verifying a logic model design are provided by first dividing the logic model design into two or more logic portions. The various model portions can then realized to form various realized logic portions. A first realized logic portion can then be wrapped and formally verified against its respective model. The wrapper can then be verified by first applying the wrapper to a second logic model portion and a second realized logic portion, then formally verifying them against each other. The resulting output can then be used to prove wrapper correctness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.