Method and system for multiplier optimization
US7567998B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Jun 29, 2005 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Oct 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49942
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein is a method and system for multiplier optimization. A gate count savings that does not introduce additional quantization error can be achieved with this method and system. By increasing the number of digits in a multiplication result, partial products within a multiplication can be truncated. When the multiplication result is used in a subsequent operation, the gates required for the increased number of digits in the multiplication result can be made less than the gates saved within the multiply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.