Automated hardware parity and parity error generation technique for high availability integrated circuits
US7568130B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2006 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Feb 22, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2247
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique wherein High Availability (HA) hardware is used to automatically validate control and configuration registers, e.g. automatically generate parity, detect parity errors, and report errors within software-written configuration and control registers of ASIC and IC products. Parity control logic and Masking Registers are utilized to facilitate automatic parity generation and subsequent parity error reporting. The specific location of where the error occurred can be stored to enable software to correct and/or reconfigure the registers. The HA hardware verifies the validity of control and configuration registers coupled to a bus, utilizing idle cycles in addition to valid bus cycles so there is no impact on system throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.