Method, system, and computer program product for hierarchical integrated circuit repartitioning
US7568176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2007 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Aug 29, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdown of the one or more interconnecting elements from the parent level. For each child designated to receive the pushdown of the one or more interconnecting elements, the method further includes determining a physical coverage area of the child, identifying which of the one or more interconnecting elements within the physical coverage area of the child to pushdown into the child, generating an interconnecting element pushdown list for the child, including wiring layer information, and outputting the interconnecting element pushdown list.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.