Processes providing high and low threshold p-type and n-type transistors
US7569449B1 · kind B1 · utility
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12Claims
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Key dates
| Filing date | Oct 3, 2006 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Nov 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0191
Abstract
Methods of fabricating negative-channel metal-oxide semiconductor (NMOS) devices and positive-channel metal-oxide semiconductor (PMOS) devices having complementary threshold voltages are described. Elements of lower-threshold voltage NMOS devices are formed at first locations on a substrate. Elements of higher-threshold voltage PMOS devices are formed at second locations on the substrate. Elements of higher-threshold voltage NMOS devices and elements of lower-threshold PMOS devices are formed by adding a same amount of p-type dopant at selected locations chosen from the first and second locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.