Semiconductor device and manufacturing method thereof
US7569467B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 6, 2006 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Aug 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76867
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a multi-layer wiring in which resistance against migration of the semiconductor device is raised to improve the yield. Semiconductor device 100 includes a first interconnect (wiring) 112, formed in a first interlayer insulating film 106 on a semiconductor substrate, not shown, a via 128 provided on the first interconnect (wiring) 112 so that the via is connected to the first interconnect (wiring) 112, and a different element containing electrically conductive film 114. The different element containing electrically conductive film is formed selectively on a site on the top of the first interconnect (wiring) 112 where the first wiring is contacted with the bottom of the via 128. The different element containing electrically conductive film contains a metal of a main component of the first interconnect (wiring) 112 and a different element different from the metal of the main component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.