Signal processing system and method
US7570068B2 · kind B2 · utility
5Cited by
39References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Oct 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R33/09
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
First and second complementary voltage signals are operatively coupled across a series circuit comprising first and second sense resistors and a circuit element therebetween. A DC bias current in the series circuit is substantially nulled, and an output signal responsive to the self-impedance of the circuit element is generated responsive at least one of a voltage across the first sense resistor and a voltage across the second sense resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.