Methods and systems for designing high resolution analog to digital converters
US7570191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2007 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Jun 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and systems for designing a high resolution analog to digital converter (ADC) by eliminating the errors in the ADC stages. An error correction architecture and method eliminate the gain error and settling error of the residue amplifier in a pipelined ADC stage. A reference voltage error correction architecture and method eliminate the reference voltage error due to the sampling action in the ADC. The gain error correction method calculates the gain error using an error amplifier and eliminates the gain error at a later stage of the ADC. The reference voltage error correction method calculates the reference voltage error using an ideal reference voltage and corrects the error at a later stage of the ADC. Therefore, the constraints of gain and settling of the residue amplifier is significantly reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.