Method and apparatus for reducing soft errors
US7570508B2 · kind B2 · utility
0Cited by
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10Claims
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Key dates
| Filing date | Dec 22, 2003 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | May 17, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing soft errors in which the method includes: assigning a plurality of nodes within a storage circuit to a predetermined state; evaluating a plurality of signals coupled to the storage circuit, where evaluating the plurality of signals enables a first node to change from its predetermined state; and actively maintaining a second node in its predetermined state, where actively maintaining the predetermined state reduces the storage circuit's susceptibility to soft errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.