Three-dimensional semiconductor memory device having a first and second charge accumulation region
US7570516B2 · kind B2 · utility
26Cited by
21References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 19, 2007 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Dec 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a sense amplifier and a decoder provided on a semiconductor substrate together with memory cells provided above the sense amplifier and the decoder. Each of the memory cells includes a channel region, in which current flows in a direction perpendicular to a surface of the semiconductor substrate, a charge accumulation region provided along the channel region, and an insulator film provided between the channel region and the charge accumulation region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.