Memory cells with power switch circuit for improved low voltage operation
US7570537B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2007 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Jul 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices. For example, in one implementation, by temporarily interrupting the connection between portions of an SRAM cell and a power source such as a reference voltage or current source, the writeability of SRAM cells can be improved. Additional read port implementations are also provided to facilitate low voltage operation. In another implementation, a power switch circuit responsive to a word line and logic signals may be used to provide such interruptions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.