Method for identifying memory bit cells and connections
US7570539B2 · kind B2 · utility
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3References
27Claims
0Family size
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Key dates
| Filing date | Feb 25, 2005 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Feb 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for identifying memory bit cells and connections for analysis of a circuit block. The method includes defining a bit pattern for each bit cell node in a bit cell. The method also includes defining a node pattern for each node in the circuit block; and matching the node patterns with the bit patterns. The bit cells and corresponding bit line connections and word line connections in the circuit block are determined based on matches found during the matching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.