Parallel processing data transfer arrangements
US7570611B2 · kind B2 · utility
5Cited by
4References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2004 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Oct 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data transfer arrangement may be used in a System on a Chip (SoC). The SoC has a processing element fabric and a logic element fabric. The two fabrics are coupled by a fabric exchange element to transfer data efficiently between the processing element fabric and the logic element fabric to facilitate parallel processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.