Derivative superposition circuit for linearization
US7570935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2006 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Aug 11, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/3252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A derivative superposition circuit for linearization includes a first active element that is provided with first to third terminals and in which the magnitude and direction of current flowing from the second terminal to the third terminal changes on the basis of the magnitude of a voltage applied between the first and second terminals; and a second active element that is provided with first to third terminals and has complementary characteristics with the first active element. The first terminals of the first and second active elements are connected to each other so that a predetermined operational bias voltage is maintained by first and second power supplies through a first impedance, and are connected to an input end through a second impedance. The third terminals of the first and second active elements are connected to an output end, and the second terminals of the first and second active elements are connected to the second power supply through a third impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.