Computer storage exception handling apparatus and method for virtual hardware system
US7571087B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 2008 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Feb 6, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a design system using virtual hardware models, a filtering manager for filtering execution results and determining which software instructions are candidates for restructuring. In some examples, illegal address range instructions are identified based on exception records and restructured software instructions may redirect memory access to an appropriate memory location thereby enabling the use of hardware device drivers in conjunction with hardware emulations, simulations or virtual models without requiring driver source code modifications. Using different filtering criteria, some or all legal and/or illegal memory access software instructions may be redirected to mapped memory locations enabling control over memory access functions. In some cases, debugging tools may be configured or altered to reduce, limit or disable exception handling trace messages, thereby improving overall processing performance by eliminating or reducing unnecessary or burdensome error or trace report generation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.