Method and apparatus for digital noise mask filtering
US7571202B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 7, 2005 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Jan 31, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for filtering spurious transitions from a digital signal is disclosed. The system includes a latch, a timer, and a logic circuit. Upon a transition of the digital signal, the latch holds the digital signal to block any additional transitions and the timer, which is connected to the output of the latch, begins a timing operation that creates a filter pulse. The output of the timer is then combined with the digital signal to filter the spurious transitions that may occur after the transition of the signal. The timer is implemented as an integrator that generates a ramp signal using a stable current source and a comparator that trips when the ramp signal passes a threshold. Use of the integrator and comparator saves space and reduces the system's operating current compared to the conventional approach.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.