Network device/CPU interface scheme
US7571216B1 · kind B1 · utility
44Cited by
6References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2003 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Apr 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for implementing a CPU/Network Device Interface that reduces the CPU involvement in managing the interface. New data structures in shared memory that are either read-only or write-only by CPU allow the CPU to efficiently utilize techniques such as write-posting and cache prefetching. Additionally, hardware-assisted packet transmission and high-level packet flow control reduce the burden on the CPU. A fair allocation system assures fair access to the receive interface by multiple line cards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.