Core clock alignment circuits that utilize clock phase learning operations to achieve accurate clocking of data derived from serial data streams having different relative skews
US7571267B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2006 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Feb 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Core clock alignment circuits include a serial-in parallel-out (SIPO) data processing circuit, which is configured to generate a plurality of lanes of deserialized data in response to a corresponding plurality of lanes of serialized data. The SIPO data processing circuit is further configured to generate a plurality of recovered clock signals from corresponding ones of the plurality of lanes of serialized data. These recovered clock signals may be out-of-phase relative to each other. The devices also include a plurality of lane FIFOs, which are configured to receive respective ones of the plurality of lanes of deserialized data and respective ones of the plurality of recovered clock signals at write ports thereof. A core clock alignment circuit is provided, which may be electrically coupled to the plurality of lane FIFOs. The core clock alignment circuit is configured to perform clock phase learning operations to generate a core clock in response to detecting a plurality of training state headers received by the plurality of lane FIFOs. This core clock may be provided to read ports of the plurality of lane FIFOs to thereby synchronize FIFO read operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.