Reduced memory traffic via detection and tracking of temporally silent stores
US7571286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2006 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Nov 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores. When a memory store, comprising an address and a data value, to a cache is detected, a determination is made that a cache line in the cache contains a same address as the address in the memory store. A determination is then made that a tentative cache line invalidate signal for the cache line was previously sent to other data processing systems in the network to tentatively invalidate the cache line. If the memory store is a temporally silent store, a cache line revalidate signal is sent to the other data processing systems to clear the tentative invalidate signal for the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.