Eliminating receiver clock drift caused by voltage and temperature change in a high-speed I/O system that uses a forwarded clock
US7571340B2 · kind B2 · utility
24Cited by
9References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2006 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Oct 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Integrated circuits include clock deskew circuitry. The clock deskew circuitry, at the receiver side, receives data signals and a forwarded clock signal from a transmitter. The receiver detects a clock drift in a receiver clock tree, and transmits the detected clock drift to the transmitter. Based on the detected clock drift, the transmitter adjusts the timing of the transmitted signals so that the center of the data eye is aligned with the clock edge at the output of the receiver clock tree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.